Semiconductor memory device performing partial self refresh and memory system including same

ABSTRACT

A semiconductor memory device capable of performing a partial self refresh and semiconductor memory system including same is provided. The semiconductor memory device includes: a memory circuit including a memory array; a skip address storage unit storing an address of an excluded region not requiring refresh in the memory array as a skip address; a refresh address generator providing an address of a region of the memory array requiring refresh as a refresh address; and an address comparator receiving and comparing the skip address and refresh address, and providing a refresh control signal to the memory circuit based on the comparison.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No.10-2009-0131201 filed on Dec. 24, 2009, the subject matter of which ishereby incorporated by reference.

BACKGROUND

The inventive concept relates to semiconductor memory devices capable ofperforming a partial self refresh, and semiconductor memory systemsincluding this type of memory device. More particularly, the inventiveconcept relates to semiconductor memory devices not performing (or“excluding”) self refresh for a specific region identified by an addresswhile performing self refresh for other regions, as well as memorysystems including same.

Data is stored in memory cells of many volatile semiconductor memorydevices, such as dynamic random access memory (DRAM), by storing acorresponding level of electrical charge on a capacitor. This chargemust be periodically restored (or “refreshed”) to avoid the loss ofdata, since the stored charge inevitably leaks from the capacitor overtime.

Accordingly, some form of refresh operation must be used in conjunctionwith volatile semiconductor memory devices and constituent memorysystems.

SUMMARY

Embodiments of the inventive concept provide semiconductor memorydevices excluding self refresh in a specific region defined by anaddress, while performing self refresh in other regions. Embodiments ofthe inventive concept also provide semiconductor memory systemsincluding this type of semiconductor memory device.

According to an aspect of the inventive concept, there is provided asemiconductor memory device including: a memory circuit including amemory array; a skip address storage unit storing an address of anexcluded region not requiring refresh in the memory array as a skipaddress; a refresh address generator providing an address of a region ofthe memory array requiring refresh as a refresh address; and an addresscomparator receiving and comparing the skip address and refresh address,and providing a refresh control signal to the memory circuit based on aresult of the comparison.

The memory circuit may receive the refresh control signal and therefresh address and refresh the region of the memory array correspondingto the refresh address in response to activation of the refresh controlsignal.

The memory circuit may further include a row decoder, a column decoder,and a sense amplifier and receive an external command signal, addresssignal, and data signal.

The skip address storage unit may receive a command signal and anaddress signal and store the address signal as a skip address if thecommand signal is a mode register write signal.

The skip address storage unit may receive an external command signal andan address signal and store the first and last addresses of an excludedregion in the memory array of the memory circuit as a skip address ifthe command signal is a mode register write signal.

Meanwhile, the refresh address generator may include a refresh addresscounter that receives an external command signal, and sequentiallyincreases the refresh address signal and outputs the refresh address ifthe command signal is a self refresh-start command signal.

The address comparator may deactivate the refresh control signal if therefresh address corresponds to the excluded region in the memory arraybased on the comparison between the skip address and the refresh addressor activate the refresh control signal if the refresh addresscorresponds to the region requiring self refresh in the memory arraybased on the comparison between the skip address and the refreshaddress.

In addition, the skip address storage unit may receive an externalcommand signal and address signal, store the first address of anexcluded region in the memory array and an address subsequent to thelast address of the excluded region of the memory array as a skipaddress if the command signal is a mode register write signal. Theaddress comparator may compare the skip address with the refresh addressand toggle the refresh control signal if the skip address is identicalto the refresh address.

The semiconductor memory device may further include a self refreshcontroller that receives a command signal and an address signal, andoutputs the address signal to the skip address storage unit if thecommand signal is a mode register write signal, and activates a refreshenable signal and outputs the activated refresh enable signal to therefresh address generator if the command signal is a self refresh-startcommand signal, wherein the skip address storage unit stores the addresssignal that is received from the self refresh controller as a skipaddress, and wherein the refresh address generator outputs an address ofa region in the memory array to be refreshed as the refresh address inresponse to the activation of the refresh enable signal received fromthe self refresh controller.

According to another aspect of the inventive concept, there is provideda semiconductor memory system including: a semiconductor memory device;and a memory controller providing a command signal, an address signal,and a data signal to the semiconductor memory device to control thesemiconductor memory device, wherein the semiconductor memory deviceincludes: a memory circuit including a memory array; a skip addressstorage unit storing an address of an excluded region in the memoryarray as a skip address; a refresh address generator providing anaddress of a region of the memory array to be refreshed as a refreshaddress; and an address comparator receiving and comparing the skipaddress and refresh address, and providing a refresh control signal tothe memory circuit based on a result of the comparison.

If an excluded region is defined in the semiconductor memory device, thememory controller may output the mode register write command signal asthe command signal and the address of the excluded region as the addresssignal.

In addition, the memory controller may output the self refresh-startcommand signal as the command signal to the semiconductor memory deviceif the semiconductor memory device needs to be self-refreshed. Therefresh address generator may output the refresh address in response tothe self refresh-start command signal.

The semiconductor memory system may further include an imaging processorproviding temporary data related to the encoding or decoding of an imagesignal to the memory controller, wherein the memory controller providesa mode register write command signal as the command signal and theaddress of a region of the memory array in which the temporary data isstored as the address signal when the temporary data is input from theimaging processor.

The imaging processor may be a H.264 processor or a digital signalprocessor.

The semiconductor memory system may further include a microprocessorrequesting that the memory controller read data from or write data tothe semiconductor memory device, wherein the microprocessor generates askip signal based on whether or not the self refresh of data input tothe memory controller is required, and provides the skip signal to thememory controller, wherein the memory controller provides the moderegister write command signal as the command signal and the address of aregion in the memory array in which data received from themicroprocessor is stored as the address signal in response to activationof the skip signal.

According to another aspect of the inventive concept, there is provideda method of performing self refresh of a semiconductor memory device,the method including: storing an address of an excluded region notrequiring refresh in a memory array as a skip address; providing anaddress of a region in a memory array to be refreshed as a refreshaddress; comparing the skip address with a refresh address and providinga refresh control signal based on a result of the comparison; andrefreshing the region of the memory array corresponding to the refreshaddress in response to activation of the refresh control signal.

The method may further include receiving a command signal and addresssignal, wherein the storing of the address of a excluded region as theskip address includes storing the address signal as the skip address ifthe command signal is a mode register write signal, and the providing ofthe address of the region to be refreshed as the refresh addressincludes activating a refresh enable signal if the command signal is aself refresh-start command signal; and providing the refresh address inresponse to the activation of the refresh enable signal.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the inventive concept will be more clearly understoodfrom the following detailed description taken in conjunction with theaccompanying drawings in which:

FIG. 1 is a block diagram of a semiconductor memory device according toan embodiment of the inventive concept;

FIG. 2 is a block diagram of a semiconductor memory device according toanother embodiment of the inventive concept;

FIG. 3 is a block diagram of a semiconductor memory device according toanother embodiment of the inventive concept;

FIG. 4 is a block diagram of a semiconductor memory system according toan embodiment of the inventive concept;

FIG. 5 is a block diagram of a semiconductor memory system according toanother embodiment of the inventive concept;

FIG. 6 is a block diagram of a semiconductor memory system according toanother embodiment of the inventive concept;

FIG. 7A shows a conventional partial self refresh operation;

FIG. 7B shows a partial self refresh operation according to anembodiment of the inventive concept;

FIG. 8 is a block diagram of a computing system including asemiconductor memory system, according to an embodiment of the inventiveconcept; and

FIG. 9 is a flowchart illustrating a method of performing self refreshof a semiconductor memory device, according to an embodiment of theinventive concept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The attached drawings illustrate certain exemplary embodiments of theinventive concept and may be referred to in order to gain a sufficientunderstanding of the inventive concept, the merits thereof, and theobjectives accomplished by the implementation of the relatedembodiments. Throughout the written description and drawings, likereference numbers and labels are used to denote like or similarelements.

FIG. 1 is a block diagram of a semiconductor memory device 100 accordingto an embodiment of the inventive concept. Referring to FIG. 1, thesemiconductor memory device 100 generally comprises a self refreshcircuit 110 and a memory circuit 120. In this regard, the memory circuit120 may be a dynamic random access memory (DRAM).

The term “self refresh” denotes a refresh operation performed internalto the semiconductor memory device during a predetermined period of timein order to maintain data stored in a memory cell capacitor. Thispredetermined time period typically occurs while the semiconductormemory device is in an idle or waiting state. During a self refreshoperation, all input signals except for an external control signal aredeactivated, and a refresh address signal for performing the selfrefresh operation and a refresh command signal may be generated in thesemiconductor memory device 100. Self refresh may be performed in a lowpower mode, a battery back-up mode, or the like.

The self refresh circuit 110 of FIG. 1 receives a command signal CMD andan address signal ADDR, generates a refresh control signal REF_CON and arefresh address REF_ADDR according to the command signal CMD and theaddress signal ADDR, and outputs the refresh control signal REF_CON andthe refresh address REF_ADDR. The memory circuit 120 may perform a selfrefresh operation according to the refresh control signal REF_CON andthe refresh address REF_ADDR, which are received from the self refreshcircuit 110.

Referring to FIG. 1, in the self refresh circuit 110 according to thepresent embodiment, the refresh unit is not a bank or array. A partialself refresh operation may be performed for each address of the memorycircuit 120. The configuration and operation of the self refresh circuit110 will be described in more detail with reference to FIGS. 2 and 3.

The memory circuit 120 of FIG. 1 receives the refresh control signalREF_CON and the refresh address REF_ADDR from the self refresh circuit110 and refreshes a memory region corresponding to the refresh addressREF_ADDR in response to the activation of the refresh control signalREF_CON.

That is, if the refresh control signal REF_CON that is received from theself refresh circuit 110 is activated, the memory circuit 120 ignoresthe command signal CMD, the address signal ADDR, and a data signal DATA,and activates a word line that is designated as the refresh addressREF_ADDR that is received from the self refresh circuit 110 to perform arefresh operation of the memory circuit 120. The refresh operation ofthe memory circuit 120 performed by activating the word line is wellknown by those of ordinary skill in the art, and therefore detaileddescriptions thereof will be omitted here.

On the other hand, if the refresh control signal REF_CON that isreceived from the self refresh circuit 110 is deactivated, the memorycircuit 120 does not perform the refresh operation, but performs readand write operations according to the command signal CMD, the addresssignal ADDR, and the data signal DATA. The read and write operations ofthe memory circuit 120 are well known by those of ordinary skill in theart, and therefore detailed descriptions thereof will be omitted here.

The memory circuit 120 is any memory circuit that is used in asemiconductor memory device and may include a memory array (not shown)including memory cells, a row decoder (not shown), a column decoder (notshown), and a sense amplifier (not shown). The memory array, the rowdecoder, the column decoder, and the sense amplifier are commonly usedin a memory circuit, and the configuration and operation thereof arewell known by those of ordinary skill in the art, and therefore detaileddescriptions thereof will be omitted here.

FIG. 2 is a block diagram of a semiconductor memory device 200 accordingto an embodiment of the inventive concept. Referring to FIG. 2, thesemiconductor memory device 200 comprises a self refresh circuit 210 anda memory circuit 220. The memory circuit 220 may have a similarconfiguration and operation to the memory circuit 120 of FIG. 1. Theself refresh circuit 210 of FIG. 2 may be an example of the self refreshcircuit 110 of FIG. 1.

As shown in FIG. 2, the self refresh circuit 210 may include a skipaddress storage unit 211, a refresh address generator 212, and anaddress comparator 213.

Referring to FIG. 2, the skip address storage unit 211 may store anaddress of an excluded region in the memory array (not shown) of thememory circuit 220 as a skip address SKIP_ADDR. The skip address storageunit 211 receives an external command signal CMD and address signalADDR. If the external command signal CMD is a mode register writesignal, the skip address storage unit 211 stores the received addresssignal ADDR as a skip address. The command signal CMD and address signalADDR may be output from a memory controller that is disposed external tothe semiconductor memory device 200. The skip address SKIP_ADDR may be arow address of the memory array.

The skip address storage unit 211 may store the first and last addressesof the excluded region among the memory array (not shown) of the memorycircuit 220 as a skip address SKIP_ADDR. That is, the skip addressstorage unit 211 according to the illustrated embodiment of FIG. 2 doesnot store all addresses belonging to the “excluded region” not requiringself refresh, but only the first and last addresses of the excludedregion to reduce the amount of the skip address SKIP_ADDR stored in theskip address storage unit 211. Accordingly, the storage capacity of theskip address storage unit 211 may be relatively low.

Meanwhile, according to another embodiment, the skip address storageunit 211 may store the first address of the excluded region and anaddress subsequent to the last address of the excluded region, i.e., thefirst address of a subsequent region requiring self refresh as a skipaddress SKIP_ADDR.

The skip address storage unit 211 may output the stored skip addressSKIP_ADDR to the address comparator 213.

Referring to FIG. 2, the refresh address generator 212 receives anexternal command signal CMD. If the received command signal CMD is aself refresh-start command signal, the refresh address generator 212generates the refresh address REF_ADDR and outputs the refresh addressREF_ADDR to the address comparator 213. In this regard, the selfrefresh-start command signal may be input as a command signal CMD whenself refresh of the memory circuit 220 is required.

The refresh address REF_ADDR is an address of a memory array to berefreshed and may be a row address of the memory array. Meanwhile, therefresh address generator 212 may output the refresh address REF_ADDRdirectly to the memory circuit 220 in addition to the address comparator213.

The refresh address generator 212 may include a refresh address counter(not shown). The refresh address counter may sequentially increase therefresh address REF_ADDR according to a refresh timing signal and outputthe refresh address REF_ADDR. For example, if the self refresh-startcommand signal is input to the refresh address generator 212, therefresh address counter (not shown) may output a first refresh addressin a first cycle of the refresh timing signal and a subsequent addressof the first refresh address as a second refresh address in a secondcycle of the refreshing timing signal. In the same manner, the refreshaddress counter (not shown) may output all of the addresses of thememory array sequentially. The refresh timing signal, which is a clocksignal having a predetermined cycle, is generated by the refresh addressgenerator 212 and input to the refresh address counter.

Referring to FIG. 2, the address comparator 213 receives the skipaddress SKIP_ADDR from the skip address storage unit 211 and receivesthe refresh address REF_ADDR from the refresh address generator 212. Theaddress comparator 213 compares the skip address SKIP_ADDR received fromthe skip address storage unit 211 with the refresh address REF_ADDRreceived from the refresh address generator 212 in order to determinewhether the memory array corresponding to the refresh address REF_ADDRgenerated by the refresh address generator 212 is required to berefreshed or not. The address comparator 213 activates or deactivatesthe refresh control signal REF_CON based on the comparison result andoutputs the activated or deactivated refresh control REF_CON to thememory circuit 220. The activation or deactivation of the output signalbased on the comparison between two addresses is well known by those ofordinary skill in the art, and therefore detailed descriptions thereofwill be omitted here. For example, a method of determining whether twoaddresses are the same or not using a plurality of XOR gates that outputa logic high signal when two input signals are the same and output alogic low signal when two input signals are different is well known inthe art.

The address comparator 213 deactivates the refresh control signalREF_CON when the refresh address REF_ADDR corresponds to an excludedregion in the memory array as a result of the comparison between theskip address SKIP_ADDR and the refresh address REF_ADDR, and outputs thedeactivated refresh control signal REF_CON to the memory circuit 220.

On the other hand, the address comparator 213 activates the refreshcontrol signal REF_CON when the refresh address REF_ADDR corresponds toan “included region” requiring self refresh in the memory array as aresult of the comparison between the skip address SKIP_ADDR and therefresh address REF_ADDR, and outputs the activated refresh controlsignal REF_CON to the memory circuit 220. If the activated refreshcontrol signal REF_CON is output to the memory circuit 220, the addresscomparator 213 may output the refresh address REF_ADDR received from therefresh address generator 212 to the memory circuit 220. Meanwhile, asdescribed above, the refresh address REF_ADDR may be directly input fromthe refresh address generator 212 to the memory circuit 220.

Meanwhile, as described above, the skip address storage unit 211 maystore the first address of the excluded region and an address subsequentto the last address of the excluded region of the memory array (notshown) as a skip address SKIP_ADDR. In this regard, the addresscomparator 213 compares the skip address SKIP_ADDR and the refreshaddress REF_ADDR. If the skip address SKIP_ADDR is identical to therefresh address REF_ADDR, the address comparator 213 toggles the refreshcontrol signal REF_CON and outputs the toggled signal.

This will now be described in some additional detail.

For example, it is assumed that the memory array of the memory circuit220 has row addresses from ‘000’ to ‘111’, and excluded regions havingrow addresses of ‘001’, ‘010’, and ‘011’ are not required to beself-refreshed. Since the skip address storage unit 211 may store thefirst address of an excluded region and an address subsequent to thelast address of the excluded region as a skip address SKIP_ADDR, theskip address storage unit 211 stores ‘001’ as the first address of theexcluded region and ‘100’ as the subsequent address to ‘011’,which isthe last address of the excluded region, as a skip address SKIP_ADDR.

If a self refresh-start command signal is input to the refresh addressgenerator 212, the refresh address generator 212 generates ‘000’ that isthe first row address of the memory array as the refresh addressREF_ADDR and outputs the refresh address REF_ADDR to the addresscomparator 213 in the first refresh cycle. The address comparator 213activates the refresh control signal REF_CON and outputs the activatedsignal since there is no skip address SKIP_ADDR that is identical to therefresh address REF_ADDR. Here, the initial state of the refresh controlREF_CON may be an activated one. The memory circuit 220 may refresh theregion of the memory array having a row address of ‘000’ according tothe input refresh address REF_ADDR in response to the activated refreshcontrol signal REF_CON.

Then, in the second refresh cycle, the refresh address generator 212sequentially increases the refresh address REF_ADDR and outputs ‘001’ asthe refresh address REF_ADDR to the address comparator 213. Since therefresh address REF_ADDR ‘001’ is identical to the skip addressSKIP_ADDR ‘001’, the address comparator 213 deactivates the refreshcontrol signal REF_CON by toggling the refresh control signal REF_CONand outputs the deactivated signal. Thus, the memory circuit 220 doesnot perform a refresh operation in response to the deactivated refreshcontrol signal REF_CON.

Then, in the third refresh cycle, the refresh address generator 212sequentially increases the refresh address REF_ADDR and outputs ‘010’ asthe refresh address REF_ADDR to the address comparator 213. Since thereis no skip address SKIP_ADDR that is identical the refresh addressREF_ADDR ‘010’, the address comparator 213 deactivates the refreshcontrol signal REF_CON without toggling the refresh control signalREF_CON and outputs the deactivated refresh control signal REF_CON.Thus, the memory circuit 220 does not perform a refresh operation.

Then, in the fourth refresh cycle, the refresh address generator 212sequentially increases the refresh address REF_ADDR and outputs ‘011’ asthe refresh address REF_ADDR to the address comparator 213. Since thereis no skip address SKIP_ADDR that is identical to the refresh addressREF_ADDR ‘011’, the address comparator 213 deactivates the refreshcontrol signal REF_CON without toggling the refresh control signalREF_CON and outputs the deactivated refresh control signal REF_CON.Thus, the memory circuit 220 does not perform a refresh operation.

Then, in the fifth refresh cycle, the refresh address generator 212sequentially increases the refresh address REF_ADDR and outputs ‘100’ asthe refresh address REF_ADDR to the address comparator 213. Since therefresh address REF_ADDR ‘100’ is identical to the skip addressSKIP_ADDR ‘100’, the address comparator 213 activates the refreshcontrol signal REF_CON by toggling the refresh control signal REF_CONand outputs the activated refresh control signal REF_CON. Thus, thememory circuit 220 may refresh the region of the memory array having arow address of ‘100’ according to the refresh address REF_ADDR.

Since the sequentially increasing refresh address REF_ADDR is not alwayscontinuously identical to the skip address SKIP_ADDR in the followingrow addresses, the refresh control signal REF_CON is in the activatedstate, and regions having a row address up to ‘111’ in the memory arraymay be refreshed.

After the external self refresh-start command signal is applied to therefresh address generator 212 and until a self refresh-stop commandsignal is later applied, the self refresh operation is repeated for aself refresh period. If the command signal CMD input to the refreshaddress generator 212 is the self refresh-stop command signal, a selfrefresh counter (not shown) of the refresh address generator 212 doesnot output the refresh address REF_ADDR any more. Accordingly, theaddress comparator 213 outputs the deactivated refresh control signalREF_CON to the memory circuit 220 to terminate the self refreshoperation.

Meanwhile, the skip address storage unit 211 may store the first andlast addresses of the excluded region in the memory array (not shown) ofthe memory circuit 220 as a skip address SKIP_ADDR. In this regard, ifthe first address of the excluded region is identical to the refreshaddress REF_ADDR, the refresh control signal REF_CON is toggled in therefresh cycle. If the last address of the excluded region is identicalto the refresh address REF_ADDR, the refresh control signal REF_CON istoggled in the subsequent refresh cycle. This is because the selfrefresh operation is started again from the address subsequent to thelast address of the excluded region. The configuration and operation ofthe address comparator 213 may vary according to the skip addressSKIP_ADDR stored in the skip address storage unit 211 as is wellunderstood by those of skilled in the art, and therefore a detaileddescriptions thereof will be omitted here.

FIG. 3 is a block diagram of a semiconductor memory device 300 accordingto another embodiment of the inventive concept. Referring to FIG. 3, thesemiconductor memory device 300 includes a self refresh circuit 310 anda memory circuit 320. The memory circuit 320 may have a similarconfiguration and operation to the memory circuit 120 of FIG. 1. Theself refresh circuit 310 of FIG. 3 may be an example of the self refreshcircuit 110 of FIG. 1.

As shown in FIG. 3, the self refresh circuit 310 may include a skipaddress storage unit 311, a refresh address generator 312, an addresscomparator 313, and a self refresh controller 314.

The self refresh controller 314 receives a command signal CMD andaddress signal ADDR. If the received command signal CMD is a moderegister write signal, the self refresh controller 314 may output thereceived address signal ADDR to the skip address storage unit 311. Ifthe received command signal CMD is a self refresh-start command signal,the self refresh controller 314 activates a refresh enable signal REF_ENand outputs the activated refresh enable signal REF_EN to the refreshaddress generator 312.

The skip address storage unit 311 may receive an address signal ADDRfrom the self refresh controller 314 and store the received address ADDRas a skip address SKIP_ADDR. The skip address storage unit 311 of FIG. 3may be similar to the skip address storage unit 211 of FIG. 2. That is,as described with reference to FIG. 2, the skip address storage unit 311may store the first and last addresses of the excluded region in thememory array (not shown) of the memory circuit 320 as the skip addressSKIP_ADDR. In addition, according to another embodiment, the skipaddress storage unit 311 may store the first address of the excludedregion and an address subsequent to the last address of the excludedregion, i.e., the first address of a subsequent region requiring selfrefresh, as the skip address SKIP_ADDR.

The refresh address generator 312 receives the refresh enable signalREF_EN from the self refresh controller 314 and outputs an address ofthe memory array to be refreshed to the address comparator 313 as therefresh address REF_ADDR in response to the activation of the refreshenable signal REF_EN. The refresh address REF_ADDR is an address of thememory array to be refreshed and may be a row address of the memoryarray. Meanwhile, the refresh address generator 312 may output therefresh address REF_ADDR directly to memory circuit 320 in addition tothe address comparator 313.

The refresh address generator 312 may include a refresh address counter(not shown). The refresh address counter (not shown) may sequentiallyincrease the refresh address REF_ADDR according to a refresh timingsignal and output the refresh address REF_ADDR. For example, if theactivated refresh enable signal REF_EN is input to the refresh addressgenerator 312, the refresh address counter (not shown) may output afirst refresh address in a first cycle of the refresh timing signal anda subsequent address of the first refresh address as a second refreshaddress in a second cycle of the refreshing timing signal. In the samemanner, the refresh address counter (not shown) may output all of theaddresses of the memory array sequentially.

Referring to FIG. 3, the self refresh circuit 313 receives a skipaddress SKIP_ADDR and a refresh address REF_ADDR, compares the skipaddress SKIP_ADDR with the refresh address REF_ADDR, and outputs arefresh control signal REF_CON based on the comparison result. In otherwords, the address comparator 313 compares the skip address SKIP_ADDRstored in the skip address storage unit 311 with the refresh addressREF_ADDR in order to determine whether the memory array corresponding tothe refresh address REF_ADDR generated by the refresh address generator312 is required to be refreshed or not. The address comparator 313activates or deactivates the refresh control signal REF_CON based on thecomparison result and outputs the activated or deactivated refreshcontrol REF_CON to the memory circuit 320. The address comparator 313 ofFIG. 3 has a similar configuration and operation to the addresscomparator 213 of FIG. 2, and therefore detailed descriptions thereofwill be omitted here.

The memory circuit 320 receives the refresh control signal REF_CON andthe refresh address REF_ADDR and refreshes a memory region correspondingto the refresh address REF_ADDR in response to the activation of therefresh control signal REF_CON. The memory circuit 320 of FIG. 3 has asimilar configuration and operation to the memory circuit 120 of FIG. 1and memory circuit 220 of FIG. 2, and therefore detailed descriptionsthereof will be omitted here.

FIG. 4 is a block diagram of a semiconductor memory system 400 accordingto an embodiment of the inventive concept. Referring to FIG. 4, thesemiconductor memory system 400 includes a semiconductor memory device410 and a memory controller 420. The semiconductor memory device 410 hasa similar configuration and operation to the semiconductor memorydevices 100, 200, and 300 of FIGS. 1 to 3, and therefore detaileddescriptions thereof will be omitted here.

The memory controller 420 of FIG. 4 may output a command signal CMD, anaddress signal ADDR, and a data signal DATA to the semiconductor memorydevice 410. If there is a excluded region in a memory array (not shown)of a memory circuit 412, the memory controller 420 outputs a moderegister write signal to the self refresh circuit 411 as a commandsignal CMD and outputs the first and last addresses of the excludedregion to the self refresh circuit 411 as an address signal ADDR. Asdescribed with reference to FIGS. 2 and 3, the self refresh circuit 411may store a skip address SKIP_ADDR in the skip address storage units 211and 311 according to the command signal CMD and the address signal ADDR.

Meanwhile, the memory controller 420 may output a mode register writesignal to the self refresh circuit 411 as the command signal CMD andoutput the first address of the excluded region and an addresssubsequent to the last address of the excluded region, i.e., the firstaddress of a subsequent region requiring self refresh to the selfrefresh circuit 411 as the skip address SKIP_ADDR.

The memory controller 420 may output the self refresh-start commandsignal to the self refresh circuit 411 as the command signal CMD if thememory circuit 412 is required to be self-refreshed. As described withreference to FIGS. 2 and 3, the self refresh circuit 411 may generatethe refresh address REF_ADDR in the refresh address generators 212 and312 and output the refresh address REF_ADDR in response to the selfrefresh-start command signal.

The operations of the self refresh circuit 411 and the memory circuit412 according to the command signal CMD, the address signal ADDR, andthe data signal DATA received from the memory controller 420 aredescribed with reference FIGS. 2 and 3, and therefore detaileddescriptions thereof will be omitted here.

FIG. 5 is a block diagram of a semiconductor memory system 500 accordingto an embodiment of the inventive concept. Referring to FIG. 5, thesemiconductor memory system 500 comprises a semiconductor memory device510, a memory controller 520, and an imaging processor 530. Thesemiconductor memory device 510 and the memory controller 520 may have asimilar configuration and operation to the semiconductor memory device410 and the memory controller 420 of FIG. 4.

The imaging processor 530 is a device capable of encoding/decoding animage signal in accordance with the control of an operating system. Inone possible embodiment, the imaging processor 530 may be a H.264processor or another digital signal processor (DSP). The imagingprocessor 530 may temporarily store data to be processed whileencoding/decoding the image signal. Thus, the data being processed bythe imaging processor 530 in the semiconductor memory device 510 is datathat does not require self refresh.

Thus, if data processing is requested by the imaging processor 530, thememory controller 520 may set (or define by corresponding address) amemory region storing the image data being processed to be an excludedregion. Accordingly, the memory controller 520 may output the moderegister write signal to the self refresh circuit 511 as the commandsignal CMD and output the address of the excluded region to the selfrefresh circuit 511. As described with reference to FIGS. 2 and 3, theself refresh circuit 511 may store the address as a skip addressSKIP_ADDR.

FIG. 6 is a block diagram of a semiconductor memory system according toanother embodiment of the inventive concept. Referring to FIG. 6, thesemiconductor memory system 600 comprises a semiconductor memory device610, a memory controller 620, and a microprocessor 630. Thesemiconductor memory device 610 and the memory controller 620 may have asimilar configuration and operation to the semiconductor memory device410 and the memory controller 420 of FIG. 4.

In certain embodiments of the inventive concept, the microprocessor 630may be a universal microprocessor and may request the memory controller620 to read data from or write data to the memory under the control ofthe operating system.

The data being processed by the microprocessor 630 in the semiconductormemory device 610 may be data stored in the semiconductor memory device610 for such a duration that self-refresh is required, or it may be datatemporarily stored in the semiconductor memory device 610 that does notrequire self-refresh. Accordingly, the microprocessor 630 may generate askip signal SKIP and output the skip signal SKIP to the memorycontroller 620. That is, the memory controller 620 may determine thatthe data (DATA) received from the microprocessor 630 is data notrequiring self refresh if the skip signal SKIP is activated, and mayalternately determine that data (DATA) received from the microprocessor630 is data requiring self refresh if the skip signal SKIP isdeactivated.

If the activated skip signal SKIP is applied, the memory controller 620sets the memory region storing the data being processed to an excludedregion since the data (DATA) received from the microprocessor 630 doesnot require self refresh. Accordingly, the memory controller 620 mayoutput the mode register write signal to the self refresh circuit 611 asthe command signal CMD and output the address of the excluded region tothe self refresh circuit 611. As described with reference to FIGS. 2 and3, the self refresh circuit 611 may store the address as a skip addressSKIP_ADDR.

FIG. 7A conceptually illustrates a conventional partial self refreshoperation. Referring to FIG. 7A, the conventional partial self refreshoperation is performed for each bank or array and cannot be applied toan operating system controlling a memory. The conventional partial selfrefresh operation may be performed with respect to a first bank Bank1, athird bank Bank3, and a fourth bank Bank4. First through third arraysarray1, array2, and array3 of each bank may be self-refreshed. In FIG.7A, dark portions indicate memory regions in which self refresh isperformed, and light portions indicate regions in which self refresh isnot performed.

FIG. 7B shows a partial self refresh operation according to anembodiment of the inventive concept. Referring to FIG. 7B, dark portionsindicate memory regions in which self refresh is performed, and lightportions indicate regions in which self refresh is not performed.Distinguished from the conventional partial self refresh operation, thepartial self refresh operation according to the present embodiment isperformed for each address unit of a memory.

FIG. 8 is a block diagram of a computing system 800 including asemiconductor memory system, according to an embodiment of the inventiveconcept. Referring to FIG. 8, the computing system 800 comprises asemiconductor memory system 810, a microprocessor 820 electricallyconnected to a bus 850, a user interface 830, and a power supply device840.

The semiconductor memory system 810 is described with reference to FIGS.1 through 5, and detailed descriptions thereof will be omitted here. Theconfiguration and operation of the microprocessor 820, the userinterface 830, and the power supply device 840 are well known by thoseof ordinary skill in the art, and therefore detailed descriptionsthereof will be omitted here. The microprocessor 820 may be the imagingprocessor 530 of FIG. 5 or the microprocessor 630 of FIG. 6. If thecomputing system 800 is a mobile device, a battery to supply anoperating voltage of the computing system 800 may further be included.

FIG. 9 is a flowchart illustrating a method of performing self refreshof a semiconductor memory device, according to an embodiment of theinventive concept. The method of performing self refresh may include:storing an address of a excluded region as a skip address (S91),outputting (or providing) an address of a region to be refreshed as arefresh address (S92), comparing the skip address with the refreshaddress and outputting a refresh control signal based on the comparisonresult (S93), and refreshing the region of the memory arraycorresponding to the refresh address in response to the activation ofthe refresh control signal (S94).

In addition, the method may further include receiving an externalcommand signal and address signal. In addition, the storing of anaddress of a excluded region as a skip address (S91) may include storingthe address signal as the skip address if the command signal is a moderegister write signal. Furthermore, the provision of an address of aregion to be refreshed as a refresh address (S92) may include activatinga refresh enable signal if the command signal is a self refresh-startcommand signal, and providing the refresh address in response to theactivation of the refresh enable signal. Descriptions of the method ofperforming the self refresh of the semiconductor memory device accordingto the present embodiment are similar to those of the semiconductormemory device with reference to FIGS. 1 through 3, and thereforedetailed descriptions thereof will be omitted here.

Of further note, the semiconductor memory device, semiconductor memorymodule, and semiconductor memory system according to the presentinventive concept may be mounted using various packages. For example,the semiconductor memory device, semiconductor memory module, andsemiconductor memory system according to the present inventive conceptmay be mounted using packages such as package on package (PoP), ballgrid arrays (BGAs), chip scale packages (CSPs), plastic leaded chipcarrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack,die in wafer form, chip on board (COB), ceramic dual in-line package(CERDIP), plastic metric quad flat pack (MQFP), thin quad flatpack(TQFP), small outline integrated circuit (SOIC), shrink small outlinepackage (SSOP), thin small outline package (TSOP), thin quad flat pack(TQFP), system in package (SIP), multi chip package (MCP), wafer-levelfabricated package (WFP), and wafer-level processed stack package (WSP).

While the inventive concept has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodthat various changes in form and details may be made therein withoutdeparting from the scope of the following claims.

1. A semiconductor memory device comprising: a memory circuit comprisinga memory array; a skip address storage unit configured to store anaddress of an excluded region of the memory array not requiring refreshas a skip address; a refresh address generator configured to provide anaddress of a region of the memory array requiring refresh as a refreshaddress; and an address comparator configured to receive and compare theskip address and the refresh address, and provide an activated ordeactivated refresh control signal to the memory circuit in response tothe comparison of the skip address and refresh address.
 2. Thesemiconductor memory device of claim 1, wherein the memory circuit isconfigured to receive the refresh control signal and the refreshaddress, and refresh the region of the memory array corresponding to therefresh address in response to the activated refresh control signal. 3.The semiconductor memory device of claim 1, wherein the skip addressstorage unit is further configured to receive a command signal and anaddress signal, and store the address signal as a skip address if thecommand signal is a mode register write signal.
 4. The semiconductormemory device of claim 1, wherein the address comparator is furtherconfigured to deactivate the refresh control signal if the refreshaddress corresponds to the excluded region in the memory array based onthe comparison of the skip address and refresh address, or activate therefresh control signal if the refresh address corresponds to the regionrequiring refresh in the memory array based on the comparison of theskip address and refresh address.
 5. The semiconductor memory device ofclaim 1, further comprising: a self refresh controller configured toreceive a command signal and an address signal, and provide the addresssignal to the skip address storage unit if the command signal is a moderegister write signal, activate a refresh enable signal and provide theactivated refresh enable signal to the refresh address generator if thecommand signal is a self refresh-start command signal, wherein the skipaddress storage unit is configured to store the address signal receivedfrom the self refresh controller as a skip address, and the refreshaddress generator is further configured to provide an address of theregion in the memory array requiring refresh as the refresh address inresponse to activation of the refresh enable signal received from theself refresh controller.
 6. A semiconductor memory system comprising: asemiconductor memory device; and a memory controller configured tocontrol the semiconductor memory device by providing at least a commandsignal, an address signal, and a data signal to the semiconductor memorydevice, wherein the semiconductor memory device comprises: a memorycircuit comprising a memory array; a skip address storage unitconfigured to store an address of an excluded region of the memory arraynot requiring refresh as a skip address; a refresh address generatorconfigured to provide an address of a region of the memory arrayrequiring refresh as a refresh address; and an address comparatorconfigured to receive and compare the skip address and the refreshaddress, and provide an activated or deactivated refresh control signalto the memory circuit in response to the comparison of the skip addressand refresh address.
 7. The semiconductor memory system of claim 6,further comprising: an imaging processor configured to provide temporarydata related to the encoding/decoding of an image signal to the memorycontroller, wherein the memory controller is further configured toprovide a mode register write command signal as the command signal, andan address of a region of the memory array in which the temporary datais stored as the address signal when the temporary data is provided fromthe imaging processor.
 8. The semiconductor memory system of claim 6,further comprising: a microprocessor configured to request that thememory controller read data from or write data to the semiconductormemory device, generate a skip signal based on whether the data providedto the memory controller requires refresh, and provide the skip signalto the memory controller, wherein the memory controller is furtherconfigured to provide the mode register write command signal as thecommand signal and provide the address of a region in the memory arrayin which data received from the microprocessor is stored as the addresssignal in response to activation of the skip signal.
 9. A method ofperforming self refresh of a semiconductor memory device, the methodcomprising: storing an address of an excluded region in a memory arraynot requiring refresh as a skip address; providing an address of aregion in the memory array requiring refresh as a refresh address;comparing the skip address to the refresh address, and providing arefresh control signal based on a result of the comparison; andrefreshing the region of the memory array corresponding to the refreshaddress in response to activation of the refresh control signal.
 10. Themethod of claim 9, further comprising: receiving a command signal andaddress signal, wherein the storing the address of the excluded regionas the skip address comprises storing the address signal as the skipaddress if the command signal is a mode register write signal, and theproviding the address of the region to be refreshed as the refreshaddress comprises activating a refresh enable signal if the commandsignal is a self refresh-start command signal; and providing the refreshaddress in response to activation of the refresh enable signal.
 11. Themethod of claim 10, further comprising: receiving temporary data from animaging processor related to encoding/decoding of an image signal;providing a mode register write command signal as the command signal,and an address of a region of the memory array in which the temporarydata is stored as the address signal.
 12. The method of claim 10,further comprising: receiving a request to write data to thesemiconductor memory device; generating the skip signal based on whetherthe data to be written requires refresh; providing the mode registerwrite command signal as the command signal and the address of a regionin the memory array to which the data is to be written as the addresssignal response to activation of the skip signal.